The forming process which is now widely used for fabricating multilayer glass-ceramic substrates suitable for integrated circuit packages comprises tape casting. That process contemplates nine general steps:
(1) a glass forming batch of a desired composition is melted;
(2) that melt is cooled to a glass;
(3) that glass is comminuted to a very fine particle size (called frit);
(4) that frit is blended into an aqueous and/or organic binder/vehicle to form a slip or slurry;
(5) that slurry is deposited (usually through doctor blading) as a layer onto a thin carrier film (normally of an organic);
(6) that layer is dried;
(7) that dried layer (called tap) is removed from the carrier film;
(8) several of those layers are stacked to form a laminate; and
(9) that stack is fired to sinter the frit particles together into an integral body and subsequently cause the glass to crystallize in situ to a glass-ceramic.
In modern multilayered co-fired substrate systems, holes are punched or otherwise formed in the dried tape (termed vias) to allow connections to be made between layers, the tape is metallized with conductor and resistor patterns, and the laminate subsequently fired. The resulting multilayer package constitutes an electronic system capable of supporting several complex silicon chips on the bottom and top surfaces thereof.
Whereas Al.sub.2 O.sub.3 has comprised the material most generally utilized in the production of ceramic substrates for integrated circuit packages, Al.sub.2 O.sub.3 is subject to certain disadvantages, as will be explained below.
As the integrated circuit device becomes more complex, i.e., greater numbers of active electronic elements being packaged onto a silicon chip, a higher proportion of the system signal response time is needed to transmit signals between chips or to and from an operating application. Increased interconnect signal speed and integrity can be accomplished by shortening the signal path between chips, by using a ceramic material having improved electrical properties, i.e., having a lower dielectric constant and lower dissipation factor, and by reducing the resistance of the signal conductor and decreasing noise. Spacing the chips more closely demands very fine and closely-spaced signal lines and multilayer packages with fine vias. The combination of surface smoothness and flatness with close dimensional control becomes extremely critical for satisfactory fine line metallization and via registration. Although substrates and multilayer packages prepared from Al.sub.2 O.sub.3 can be ground and polished to a smooth flat surface, the combination of difficulty in machining and the high thermal shrinkage of Al.sub.2 O.sub.3 (.apprxeq.18%) has presented problems in securing high density via and pad registration. Furthermore, the relatively high dielectric constant of Al.sub.2 O.sub.3 at ambient temperature (.apprxeq.9-10) limits the capability to space the signal lines very close together, while avoiding cross talk and noise, and also retards the speed of the signal itself. Moreover, the linear coefficient of thermal expansion of Al.sub.2 O.sub.3 is much higher than that of silicon, thus hazarding problems in securing a firm bond therebetween.
Finally, another major drawback in the use of Al.sub.2 O.sub.3 in integrated circuit packages resides in the need for employing highly refractory metals such as molybdenum and tungsten for metallization because of the high firing temperatures required for sintering Al.sub.2 O.sub.3 (.gtoreq.1500.degree. C.). Hence, whereas the electrical resistivities of molybdenum and tungsten are relatively low, they are substantially higher than those of copper, gold, and silver; moreover, molybdenum and tungsten must be plated with gold prior to soldering.
Therefore, the principal objective of the present invention was to develop a new ceramic substrate for multilayer packages exhibiting properties superior to those of Al.sub.2 O.sub.3 for that application; viz., a lower dielectric constant (&lt;5), a sintering temperature below 1000.degree. C., a smooth flat surface without additional grinding and polishing, and enhanced dimensional control for the location of vias and pads.